As the minimum feature size achievable in semiconductor manufacturing decreases, the number of devices that can be formed in a given area increases with the inverse square of this feature size. As the areal density of devices is raised, both the device size and inter-device distances must shrink accordingly. At the same time the maximum size of a chip which can be economically produced has continuously increased. This has lead to an unprecedented increase in the complexity of chips and a need for the rapid movement of large amounts of data both within and between adjacent chips and from the chips to the world beyond. This has lead to numerous levels of interconnect on a chip as well as the requirement for higher and higher input/output connections.
One design improvement to address problems listed above includes the use of optical communication instead of electrical communications between devices on a chip and between chips. Semiconductors other than silicon are desirable to form highly effective optical communication structures. Semiconductor materials such as gallium arsenide (GaAs) can easily convert electrical signals to optical and optical to electrical. It would therefore be desirable to connect a portion of silicon semiconductor to a GaAs interface. A useful technique to couple a semiconductor such as GaAs to silicon includes epitaxially growing GaAs areas on silicon chips. One problem with this approach is that the lattice constant of GaAs does not match the lattice constant of silicon, thus causing strain or defects at the silicon/GaAs interface. Although silicon and GaAs are used as an example, interfaces between other semiconductor materials pose similar lattice mismatch problems.
What is needed is an improved method to form an epitaxial layer of semiconductor of one type over a semiconductor of another type to reduce lattice mismatch. In one specific embodiment, what is needed is a method to form a GaAs layer on a silicon surface with improved interfacial characteristics.